Plating method

ABSTRACT

A plating method according to the present invention is capable of plating a substrate with a plated film of a metal such as copper or the like with high adhesion to a seed layer without producing voids in the plated film at a high throughput, not only in recesses having a large width and a small aspect ratio, but also in recesses having a small width and a large aspect ratio, even when relatively narrow recesses and relatively broad recesses are co-present in the substrate. The plating method is performed by preparing a substrate having a relatively narrow recess and a relatively broad recess defined in a surface thereof, performing first plating under plating conditions for filling a metal in the narrow recess, and then performing second plating under plating conditions for filling a metal in the broad recess.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a plating method of filling finerecesses formed in a substrate such as a semiconductor wafer or the likewith a metal to form an interconnect circuit, and more particularly to aplating method of plating a substrate with a plated film with highadhesion without producing voids in the plated film even when relativelynarrow recesses and relatively broad recesses are co-present in thesubstrate.

[0003] 2. Description of the Related Art

[0004] In recent years, copper has widely been used as an interconnectmaterial for use in semiconductor devices. One general process forforming interconnects of copper is a damascene process in which finerecesses such as via holes, trenches, etc. are formed in an insulatingfilm formed on a substrate, and then an interconnect metal such ascopper or the like is deposited on the insulating film, after which anyextra interconnect metal is removed by CMP or the like.

[0005] According to the damascene process, before an interconnect metalsuch as copper or the like is deposited, a barrier layer such as of TaN,Ta, or the like for preventing copper atoms from being diffused into aninsulating film is formed on the surfaces of the substrate and therecesses. Then, if copper is to be deposited by performingelectroplating, a seed layer serving as a current supply layer forelectroplating is formed on the barrier layer on the surfaces of thesubstrate and the recesses. The seed layer is generally formed by PVD orCVD. PVD is widely used as it can form a seed layer capable of highadhesion to the barrier layer.

[0006] Heretofore, the following problems have arisen in forming a seedlayer on a surface of a recess: If a recess has a broad width and asmall aspect ratio, then a seed layer can uniformly be formeduninterruptedly on the entire surface of the recess. However, if a seedlayer is formed by anisotropic PVD on a surface of a recess that has anarrow width and a large aspect ratio, then an amount of the seed layermaterial deposited on the sidewall of the recess is reduced, and theseed layer formed on the sidewall of the recess is made thin. If thewidth of the recess is narrower and the aspect ratio is larger, then theseed layer deposited at the opening of the recess overhangs the opening,reducing the area of the opening.

[0007] Even when an attempt is made to embed metal (plated film) in arecess having such a seed layer by electroplating, the opening of therecess is closed by the metal before the metal is embedded in therecess, leaving voids in the metal embedded in the recess.

[0008] It is conceivable that the film thickness of the seed layer maybe reduced in order to achieve the enough area of the opening of therecess. If the film thickness of the seed layer is reduced, however, thefilm thickness of the seed layer formed on the sidewall of the recess isfurther reduced, eventually causing other problems in that the seedlayer is discontinued and includes a portion whose resistance isextremely large. If electroplating is performed onto the surface of asubstrate having a recess covered with such a discontinuous seed layer,no plated film is deposited on the discontinuous region of the seedlayer, tending to form voids, which are in contact with the sidewall ofthe recess, within the metal that is embedded in the recess.

[0009] For the above reasons, it is necessary to perform electroplatingof good adhesion on a substrate, which has a recess having a largeaspect ratio, while avoiding both the generation of voids caused withinmetal by the closure of the opening of the recess and the generation ofvoids caused within metal by the discontinuity of a seed layer.

[0010] There has been disclosed a technique for solving the aboveproblems by reinforcing an incomplete ultra-thin seed layer formed in arecess with a metal (plated film) formed by performing conformal platingusing a plating solution containing complex copper ions, thus producinga current supply layer, and then performing electroplating to embed ametal in the recess (see U.S. Pat. No. 6,197,181 and Japanese laid-openpatent publication No. H6-349952).

[0011] Similarly, there has also been disclosed a technique forreinforcing a seed layer with a metal (plated film) that is formed byperforming electroless plating (see Japanese laid-open patentpublication No. H7-193214, U.S. Pat. No. 5,913,147, and IEEE 2001, pages30 through 32, pages 33 through 34, and pages 277 through 279).

[0012] However, even when a seed layer is reinforced by a metal (platedfilm) formed by performing conformal plating, if the adhesion of thereinforced metal to the barrier layer is insufficient, then the problemof a migration that occurs from use cannot be said as being solvedthough an interconnect appears to be formed entirely in the recessimmediately after the plating. This is the reason why the abovetechniques have not been practical in the field of semiconductorfabrication.

[0013] A process of plating copper or the like directly on a barrierlayer without using a seed layer has also been developed. However, thereis a limitation on barrier layer materials that are used, and theprocess is not sufficiently reliable.

[0014] Recently, there are available substrates in which relativelynarrow recesses and relatively broad recesses are co-present. There hasbeen a demand for embedding a metal free of voids therein with increasedadhesion to a barrier layer, in a recess having a narrow width and alarge aspect ratio in such a substrate.

[0015] The present invention has been made in view of the abovedrawbacks. It is an object of the present invention to provide a platingmethod of plating a substrate with a plated film of a metal such ascopper or the like with high adhesion to a seed layer without producingvoids in the plated film at a high throughput, not only in recesseshaving a broad width and a small aspect ratio, but also in recesseshaving a narrow width and a large aspect ratio, even if relativelynarrow recesses and relatively broad recesses are co-present in thesubstrate.

SUMMARY OF THE INVENTION

[0016] According to the present invention, a substrate having arelatively narrow recess and a relatively broad recess defined in asurface thereof is prepared, first plating is performed under platingconditions for filling a metal in the narrow recess, and then secondplating is performed under plating conditions for filling a metal in thebroad recess.

[0017] With the recent advance in PVD technology and technologicaldevelopments such as atomic layer deposition, it is becoming possible toform a complete seed layer even in recesses having a narrow width and ahigh aspect ratio. According to the present invention, on the premisethat a complete seed layer has been formed, plating conditions suitablefor embedding a metal in narrow recesses and plating conditions suitablefor embedding a metal in broad recesses are appropriately changed toform a void-free plated metal film with high adhesion to the seed layerin the recesses.

[0018] For example, plating under plating conditions for a relativelyhigh bottom-up capability is suitable for embedding a metal in narrowrecesses, and plating under plating conditions for a relatively highleveling capability is suitable for embedding a metal in broad recesses.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a cross-sectional view schematically showing animpregnation plating apparatus which is preferably used in a platingmethod according to the present invention;

[0020]FIGS. 2A through 2C are diagrams showing different current recipesupon plating;

[0021]FIGS. 3A through 3D are cross-sectional views of different platedfilms after first plating in Example 1; and

[0022]FIGS. 4A through 4C are cross-sectional views of different platedfilms after second plating in Example 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] A substrate such as a semiconductor wafer or the like to beplated by a plating method according to the present invention has amixture of relatively narrow recesses and relatively broad recesses inits surface. The narrow recesses in the substrate have a width, forexample, less than 0.2 μm. The aspect ratio (AR) of the recesses havingsuch a width is often 4 or more. On the other hand, the relatively broadrecesses have a width, for example, of 0.2 μm or more and an aspectratio which is generally less than 4.

[0024] For plating the above substrate by the plating method accordingto the present invention, a barrier layer such as of TaN, Ta, or thelike is formed on the entire surface (to be plated) of a substratehaving recesses defined therein according to a common procedure, andthen a seed layer is formed according to PVD, CVD, or the like. For theformation of a seed layer, PVD is preferably used because it can form aseed layer capable of high adhesion to the barrier layer. Particularly,because of its excellent ability to form a seed layer on a sidewall of arecess, it is preferable to use a process such as self-ionizedsputtering (SIS) or self-ionized plasma sputtering (SPS).

[0025] The substrate with the seed layer formed on its surface is thensubjected to the plating method according to the present invention. Theplating method according to the present invention is basically performedby first plating under such plating conditions as to fill a metal(plated film) in relatively narrow recesses and, subsequently, secondplating under such plating conditions as to selectively fill a metal(plated film) in relatively broad recesses. The plating conditions forcarrying out the second plating may be changed in a certain range.

[0026] The first plating is performed under plating conditions for arelatively high bottom-up capability, and the second plating isperformed under plating conditions for a relatively high levelingcapability. The term “relatively” is used here for the reason that thefirst plating exhibits a certain leveling capability and the secondplating exhibits a certain bottom-up capability, and a comparisonbetween these plating indicates that the bottom-up capability is higherin the first plating than in the second plating, and the levelingcapability is higher in the second plating than in the first plating.

[0027] Several methods are available for performing the first platingwith the high bottom-up capability and the second plating with the highleveling capability. Examples of those methods are as follows:

[0028] (1) A method of changing the cathode current density (hereinafterreferred to as “current density”) upon plating thereby to change platingconditions of the first plating and the second plating. (2) A method ofchanging additives of a plating solution used upon plating thereby tochange plating conditions of the first plating and the second plating.(3) A method of changing plating solution compositions used upon platingthereby to change plating conditions of the first plating and the secondplating. (4) A method of changing relative speeds of a plating area anda plating solution upon plating thereby to change plating conditions ofthe first plating and the second plating.

[0029] According to the above-described method (1), the current densityat the time of the first plating is made lower than the current densityat the time of the second plating. In this case, it is preferable to usea plating solution containing an additive of a high bottom-up capabilityas plating solutions for use in the first plating and the secondplating. Reducing the current density during the second plating is ableto cause the additive to exhibit its bottom-up capability moreeffectively. It is determined by experimentation or the like how muchthe current density is to be lowered to increase the bottom-upcapability. If a standard copper sulfate plating solution is used, forexample, then the current density upon the first plating, which requiresthe bottom-up capability, is generally in the range from 0.1 to 1.5A/dm², and the current density upon the second plating, which requiresthe leveling capability, is generally in the range from 2 to 7 A/cm². Itis thus possible to make the current density upon the second platinggreater than the current density upon the first plating for therebyincreasing the leveling capability and making the plating rate upon thesecond plating higher than the plating rate upon the first plating toperform a time-consuming process of filling a metal in broad recesses ina short period of time.

[0030] After a metal is filled in relatively narrow recesses byperforming the first plating, a reverse electric field may be appliedfor a short period of time, as shown in FIG. 2A, to etch an overplatedfilm on the surfaces of the narrow recesses, thus removing the additivein the overplated film. The period of time for applying the reverseelectric field is generally in the range from 1 to 10 seconds, andpreferably from 1 to 4 seconds.

[0031] In FIG. 2A, the current density during the first plating and thecurrent density during the second plating are varied discontinuously.For example, as shown in FIG. 2B, the first plating and the secondplating may be performed by varying the current density so as toincrease gradually. Alternatively, as shown in FIG. 2C, the firstplating and the second plating may be performed by varying the currentdensity so as to increase linearly.

[0032] According to the above-described method (2), a plating solutioncontaining an additive of a relatively high bottom-up capability is usedas the plating solution during the first plating, and a plating solutioncontaining an additive of a relatively high leveling capability is usedas the plating solution during the second plating. For example, since acopper sulfate plating solution generally contains as additives asuppressor (precipitation suppressor: for conformal), an accelerator(increasing the bottom-up capability), and a leveler. An additiveincluding more of a component called an accelerator is used in theplating solution for the first plating, and an additive including moreof a component called a leveler is used in the plating solution for thesecond plating.

[0033] Components serving as the suppressor, components serving as theaccelerator, and components serving as the lever are well known.Representative examples of them are given as follows: Polypropyleneglycol, polyethylene glycol, their polymers, high-molecular surfactantsuch as ethylene oxide, etc. are suppressor components. Sulfur-basedorganic compounds such as dithiobis-alkane-sulfonic acids, such as4,4-dithiobisbutane sulfonic acid, 3,3-dithiobispropane sulfonic acid,etc. or their salts are accelerator components. Organic dye compoundssuch as safranine, thioflavine, Dye 300, Cy5, etc. are levelercomponents. This method may be carried out using two plating solutionscontaining different additives, or may be carried out by adding aleveler component, for example, when changing from the first plating tothe second plating.

[0034] Whether a plating solution including more of a component calledan accelerator is used as the plating solution for the first plating ornot is reflected by the concentration of sulfur in the plated film. Forexample, if copper sulfate plating is carried out using a platingsolution including more of an accelerator, then it is common for sulfuratoms to have a density of 1×10¹⁸ atoms/cm³ or more at a depth of 0.5 μmin a plated copper film having a thickness of 1 μm. If a platingsolution not including more of an accelerator is used, on the otherhand, then the density of sulfur atoms at a depth of 0.5 μm in a platedcopper film under the same conditions does not reach 1×10¹⁸ atoms/cm³ ormore.

[0035] According to the above-described method (3), furthermore, aplating solution having a high metal ion concentration and a high anionconcentration is used as the plating solution during the first plating,and a plating solution having a low metal ion concentration and a lowanion concentration is used as the plating solution during the secondplating. For example, a copper sulfate plating solution contains copperions as metal ions and sulfuric acid ions as anion ions. If a platingsolution with high concentrations of these ions is used, then thebottom-up capability is increased, and if a plating solution with lowconcentrations of these ions is used, then the leveling capability isincreased. For carrying out this method, a first plating solution havinga high metal ion concentration and a high anion concentration and asecond plating solution having a low metal ion concentration and a lowanion concentration may be prepared, and these plating solutions may beused.

[0036] According to the final method (4), the bottom-up capability andthe leveling capability are adjusted based on a change in the relativespeeds of a plating area and a plating solution upon plating. In spinplating, for example, the relative speed of the plating solution isdetermined by the rotational speed of the substrate and the speed of theplating solution jet. If the rotational speed of the substrate (thespeed in the horizontal direction with respect to the substrate) ishigh, the bottom-up capability is increased, and the leveling capabilityis lowered. If the speed of the plating solution jet (the speed in thevertical direction with respect to the substrate) is high, the bottom-upcapability is lowered, and the leveling capability is increased.Therefore, the bottom-up capability and the leveling capability can beadjusted by using these properties.

[0037] With the method according to the present invention, the abovemethods may be used singly or in combination for achieving moreappropriate bottom-up and leveling capabilities.

[0038] If an acid plating solution is used, then it is preferable tocarry out the following method when the substrate is brought into theplating solution: Specifically, an oxide film may be formed in contactwith air on the surface of a seed layer formed on the surface of asubstrate, and the oxide film may be dissolved in contact with an acidplating solution. In this case, the surface of the seed layer is etchedby the acid plating solution, and the thin seed layer may be eliminatedin extreme cases, exposing the barrier layer.

[0039] Before the substrate is brought into contact with the platingsolution, a plating voltage is applied between the substrate and theanode held in contact with the plating solution for starting to reducethe oxide film on the surface of the seed layer or deposit a plated filmfrom the time when the substrate is brought into contact with theplating solution. This method is generally referred to as hot entry.

[0040] In the hot entry, when the substrate is brought into contact withthe plating solution, a portion of the substrate first contacts theplating solution, and then the area of contact between the platingsolution and the substrate increases progressively until the entiresurface to be plated of the substrate contacts the plating solution. Asthe area of contact between the plating solution and the substratechanges, the electric resistance of the system changes greatly. In thehot entry, therefore, it is often customary to perform a voltage controlprocess for controlling the voltage applied between the substrate andthe anode at a predetermined value. If the hot entry is performed undercurrent control, then it is necessary to apply a voltage limiter toensure that no voltage higher than a preset value will be appliedbetween the substrate and the anode.

[0041] If a large voltage is set in the hot entry, then film thicknessirregularities of the plated film occur between the portion of thesubstrate which is initially brought into contact with the platingsolution and the portion of the substrate which is finally brought intocontact with the plating solution. Therefore, until the substrate isbrought into full contact with the plating solution, it is preferable touse as small a voltage as possible for preventing the seed layer frombeing dissolved.

[0042] After the hot entry is finished, if plating under the initialconditions is to be continued, the voltage control may switch to thecurrent control, but may remain in action. Particularly, if the seedlayer is thin, an initial large sheet resistance changes to a reducedresistance due to the deposition of a plated metal film on the seedlayer, making it possible to supply an appropriate current that matchesthe resistance of the seed layer. It is of course possible to use thevoltage control in the first plating and the second plating. If thecurrent density is changed in the first plating and the second plating,the voltage may be correspondingly changed in the voltage controlthereby to perform the first plating with a low current density and thesecond plating with a high current density, as with the current control.

[0043] The method according to the present invention as described abovecan be carried out using a conventional plating apparatus forsemiconductor substrates. A more preferable method is an impregnationplating method using an impregnation plating apparatus shown in FIG. 1.

[0044]FIG. 1 is a cross-sectional view schematically showing anelectrode head and a substrate holder of an impregnation platingapparatus. The impregnation plating apparatus has a swing arm 26, asubstrate holder 36, a cathode 88, and a seal member 90. Theimpregnation plating apparatus has a ball bearing 92, a housing 94having an inward protrusion 94a and a plating solution discharge port 94b, a spacer 96, an anode 98, a hollow plating solution chamber 100, anda plating solution supply pipe 102. The impregnation plating apparatusalso has a plating solution introduction pipe 104 having a platingsolution introduction port 104 a, a plating solution discharge pipe 106,a high-resistance structure 110 having a flange 110 a, narrow pipes 112,a plating power source 114, a holder 124, a vertical displacement motor132, and a ball screw 134. The impregnation plating apparatus holds asubstrate W detachably.

[0045] The electrode head of the impregnation plating apparatus has thehousing 94 coupled to the free end of the swing arm 26 by the ballbearing 92, and the high-resistance structure 110 disposed in closingrelation to a lower end opening of the housing 94. The inward protrusion94 a which projects inwardly is formed at a lower portion of the housing94, and the flange 110 a is formed at an upper portion of thehigh-resistance structure 110. The flange 110 a engages the inwardprotrusion 94 a which, with a spacer 96 interposed between the housing94 and the high-resistance structure 110, holding the high-resistancestructure 110 in the housing 94. In this manner, the hollow platingsolution chamber 10 is defined in the housing 94.

[0046] The high-resistance structure 110 is made of porous ceramics suchas alumina, SiC, mullite, zirconia, titania, cordierite, or the like, ora hard porous material such as a sintered material of polypropylene orpolyethylene, or a composite material thereof, or a woven or a non-wovenfabric. For example, alumina-based ceramics having a pore diameterranging from 30 to 200 μm, SiC having a pore diameter of 30 μm or less,a porosity ranging from 20 to 95%, and a thickness ranging from 1 to 20mm, preferably from 5 to 20 mm, or more preferably from 8 to 15 mm, isused. In this embodiment, the high-resistance structure 110 is in theform of a porous ceramics plate of alumina having a porosity of 30% andan average pore diameter of 100 μm. When the high-resistance structure110 is impregnated with a plating solution, though the porous ceramicsplate itself is an insulating material, it causes the plating solutionto enter therein in a complex pattern and follow a considerably longpath in the transverse direction thereof, providing an electricconductivity smaller than that of the plating solution.

[0047] The high-resistance structure 110 is disposed in the platingsolution chamber 100 and produces a high resistance to reduce the effectof the resistance of the seed layer to a negligible degree, thusreducing an in-plane difference between current densities due to theelectric resistance of the surface of the substrate W for increasedin-plane uniformity of the plated film.

[0048] The anode 98 is disposed in the plating solution chamber 100 andmounted on the lower surface of the plating solution introduction pipe104 disposed above the anode 98. The plating solution introduction port104 a of the plating solution introduction pipe 104 is connected to theplating solution supply pipe 102 which extends from a plating solutionsupply equipment (not shown). The plating solution discharge port 94 bon the upper surface of the housing 94 is connected to the platingsolution discharge pipe 106 which communicates with the plating solutionchamber 100.

[0049] The plating solution introduction pipe 104 is of a manifoldstructure for supplying a plating solution uniformly to the surface tobe plated. Specifically, the narrow pipes 112 communicating with theinterior of the plating solution introduction pipe 104 are connectedthereto at longitudinally spaced positions. The anode 98 and thehigh-resistance structure 110 have small holes defined therein inalignment with the narrow pipes 112. The narrow pipes 112 extend throughthose small holes and reach the lower surface of the high-resistancestructure 110 or a region near the lower surface thereof.

[0050] The plating solution introduced from the plating solution supplypipe 102 into the plating solution introduction pipe 104 passes throughthe narrow pipes 112 to a lower portion of the high-resistance structure110, passes through the high-resistance structure 110, fills the platingsolution chamber 100, causing the anode 98 to be immersed in the platingsolution. The plating solution can be discharged from the platingsolution discharge pipe 106 by evacuating the plating solution dischargepipe 106.

[0051] The anode 98 used in the above impregnation plating apparatus ismade of copper (phosphorus-containing copper) containing 0.03 to 0.05%of phosphorus in order to prevent a slime from being produced. However,the anode 98 may be made of an insoluble material.

[0052] The cathode 88 is electrically connected to the positive terminalof the plating power source 114, and the anode is electrically connectedto the negative terminal of the plating power source 114. The platingpower source 114 is arranged so as to be able to change the direction ofthe flowing current as desired.

[0053] The ball bearing 92 is suspended from the swing arm 26 via theholder 124. The sing arm 26 is vertically movable by the verticaldisplacement motor 132, which comprises a servomotor, and the ball screw134. This vertical displacement mechanism may be a pneumatic actuator.

[0054] During electroplating, the electrode head is lowered until thegap between the substrate W held by the substrate holder 36 and thehigh-resistance structure 110 becomes 0.1 to 3 mm, for example. Then,the plating solution supply pipe 102 supplies the plating solution(plating solution) to impregnate the high-resistance structure 110 withthe plating solution and fills the interior of the plating solutionchamber 100 with the plating solution from the upper surface (to beplated) of the substrate W. In this manner, the surface to be plated ofthe substrate W is plated.

[0055] The present invention will be described in detail below withrespect to examples. However, the present invention is not limited tothese examples.

[0056] In the examples, a plating solution including 150 to 250 g/l ofpentahydrate of copper sulfate, 20 to 100 g/l of sulfuric acid, 20 to 90mg/l of chlorine in terms of a basic composition was used. Additivesthat were used include 0.05 to 20 mg/l of PEG (polyethylene glycol)having a molecular weight of 20,000 as a high-molecular surfactant forsuppressing an electrodeposition reaction, 1 to 20 mg/l of3,3-dithiobispropane sulfonic acid sodium as a sulfur-based saturatedorganic compound for accelerating the electrodeposition speed, and 1 to20 mg/l of safranine as an organic dye compound for controlling theleveling of copper plating.

EXAMPLE 1

[0057] In Example 1, the first plating and the second plating werecarried out by changing current densities during plating.

[0058] (1) First, a preliminary experiment in which the concentration ofthe sulfur-based organic compound and the concentration of the organicdye compound were changed was conducted to confirm whether voids wereproduced in a metal (plated film) embedded by plating in fineinterconnect pattern recesses or not. The height of humps of the platedfilm formed by plating was also confirmed. A pattern wafer used in theexperiment had a via pattern having a diameter of 0.16 μm and a depth of0.8 μm and a via pattern having a diameter of 0.3 μm and a depth of 0.8μm, etching in a thermal oxide film. On the wafer, there was formed abarrier layer of TaN to a thickness ranging from 10 to 40 nm and a seedlayer to a thickness ranging from 60 to 150 nm by an SIS process. Thecurrent passed during plating was in the range from 0.1 A/dm² to 3A/dm². The cross section of the wafer after it was plated was confirmedwith SEM for voids in the metal.

[0059] Table 1 below shows the experimental results. With the patternhaving the diameter of 0.16 μm, the metal in the via pattern wasvoid-free only if the concentration of the sulfur-based organic compoundwas high and the concentration of the organic dye compound was low. Withthe plating solution containing 20 mg/l of the sulfur-based organiccompound and 5 mg/l of the organic dye compound, no voids were observedin the metal at a current value of in the range from 0.1 A/dM2 to 1.5A/dm², bottom voids were observed in the metal at a current value of 0.1A/dm² or less, and top voids were observed in the metal column at acurrent value in excess of 1.5 A/dm². At current values in the rangefrom 0.1 A/dm² to 1.5 A/dm², the bottom-up capability was fine, andpinch-off was suppressed. This means that the bottom-up capabilitydepends on the concentration ratio of both of additives and there is anappropriate current condition. No voids were produced in the metal forthe pattern having the diameter of 0.3 μm. TABLE 1 Amount ofsulfur-based organic compound (mg/l) 5 10 20 Amount of 5 x/∘ ∘/∘ ∘/∘organic dye 10 x/∘ x/∘ ∘/∘ compound 20 x/∘ x/∘ x/∘ (mg/l)

[0060] Diameter 0.16 μm/diameter 0.3 μm

[0061] ∘: void-free, x: voids produced

[0062] (2) Then, a pattern wafer in which a trench pattern of L/S (lineand space: trench width/trench interval)=0.18 μm/0.18 μm and L/S=0.3μm/0.3 μm were etched in a thermal oxide film having a film thickness of1.0 μm and a barrier layer and a seed layer were formed thereon wasused, and the height of humps produced on a plated film deposited byplating was confirmed. The current passed upon plating was 1.0 A/dm²,the plating time was 280 seconds, and the film was plated to a thicknesscorresponding to 1 μm in terms of a solid film. Table 2 shows theresults. It is understood from Table 2 that the height of humps is smallif the concentration of the sulfur-based organic compound is low and theconcentration of the organic dye compound is high. TABLE 2 Amount ofsulfur-based organic compound (mg/l) 5 10 20 Amount of 5  30/10 80/30120/50 organic dye 10 20/0 60/20 100/40 compound 20 10/0 30/10  70/20(mg/l)

[0063] LS: 0.18 μm/LS: 0.3 μm

[0064] The proportion of the height of humps (=b/a×100%), see a, b forFIG. 4A.

[0065] (3) Based on the preliminary experiments (1), (2), a platingexperiment was conducted on an actual pattern wafer, using a cup-typeplating apparatus for 200 mm wafers. A pattern wafer has a mixture offine patterns having a width of 0.2 μm or less and patterns having agreater width. A depth of the pattern was in a range from 0.2 to 1.0 μm.On the pattern wafer, there was formed a barrier layer of TaN to athickness ranging from 10 to 40 nm and a seed layer to a thicknessranging from 60 to 150 nm by an SIS process.

[0066] The plating solution that was used had a high sulfur-basedorganic compound concentration of 20 mg/l and a low organic dye compoundconcentration of 5 mg/l. The plating solution flowed at a rate rangingfrom 5 to 25 1/min., the plating temperature was in the range from 20 to30° C., and the wafer was rotated at a rotational speed in the rangefrom 10 to 250 rpm. Current conditions are such that according to theplating current recipe shown in FIG. 2A, the first plating was performedin the first step to embed a void-free metal in fine interconnectpatterns and the second plating was performed in the second step underconditions for a high throughput and conditions for a better in-planeuniformity of the plated film.

[0067] Specifically, in the first plating, the wafer was plated for 25to 50 seconds with an initial current value corresponding to 1.0 A/dm².At 2.0 A/dm², a reverse electric field was applied for 0.5 to 5 secondsto remove the additive from the surface. Thereafter, in the secondplating, patterns other than the fine interconnects were plated at acurrent value ranging from 2 to 7 A/dm² to form a plated film until itsfilm thickness finally reached 1 μm.

[0068]FIGS. 3A through 3D schematically show cross sections of platedfilms after the first plating. FIG. 3A shows a metal (plated film) 4 aembedded in a fine recess 2 a having a width of 2 μm or less, forexample, formed in the surface of a substrate, according to the firstplating under the condition of the current density of 0.1 A/dm² or less.In this case, since the seed layer of the fine recess 2 a is thin, acurrent is less liable to flow, and the plated film 4 a is less likelyto be precipitated. In addition, because the seed layer is etched, abottom void 6 or a side void is easily produced in the plated film 4 a.FIG. 3C shows a metal (plated film) 4 a embedded in a fine recess 2 ahaving a width of 2 μm or less, for example, according to the firstplating under the condition of the current density of 1.5 A/dm² or less.In this case, it can be seen that the pinch-off rate is higher than thebottom-up rate, making it easy to form a top void 8 in the plated film 4a. On the other hand, FIG. 3B shows a metal (plated film) 4 a embeddedin a fine recess 2 a having a width of 2 μm or less, for example,according to the first plating under the condition of the currentdensity ranging from 0.1 A/dm² to 1.5 A/dm². In this case, it can beseen that no bottom voids and no top voids are produced in the platedfilm 4 a. FIG. 3D shows a metal (plated film) 4 a embedded in abroadrecess 2 b having a width of 2 μm or more, for example, formed in thesurface of a substrate. In this case, it can be seen that a plated film6 a is formed in a nearly conformal state due to the influence of thesuppressor.

[0069]FIGS. 4A through 4C schematically show plated films after thesecond plating. FIGS. 4A through 4C illustrate that the height of humpson the plated film formed by the second plating changes depending on thewidth of the recess. Specifically, FIG. 4A shows a state in which ametal (plated film) 4 a is embedded in a fine recess 2 a having a widthof 2 μm or less, for example, according to the first plating andthereafter a plated film 4 b is formed according to the second plating.In this case, the height of a hump (=b/a×100%) of the plated film 4 bformed according to the second plating process is large. With a slightlywider recess 2 c, as shown in FIG. 4B, the height of a hump of theplated film 4 b formed according to the second plating is smaller. Witha wider recess 2 b, as shown in FIG. 4C, a concave plated film 4 b isformed by the second plating.

[0070] As described above, the first plating and the second plating areperformed under different two-step current conditions for embedding finepatterns and forming a plated film with good in-plane film thicknessuniformity at a high throughput.

EXAMPLE 2

[0071] In Example 2, the first plating and the second plating werecarried out by changing additive components during plating.

[0072] Plating was performed using two cells having plating solutionscontaining different sulfur-based organic compound and organic dyecompound concentrations with a cup-type plating apparatus for 200 mmwafers. In the first plating, a plating solution having a highsulfur-based organic compound concentration of 20 mg/l and a low organicdye compound concentration of 5 mg/l was used, and the wafer was platedfor 25 to 50 seconds with a current value corresponding to 1.0 A/dm²under the conditions of Example 1, thus embedding a metal (plated film)in a fine interconnect pattern.

[0073] In the second plating, a plating solution having a lowsulfur-based organic compound concentration of 5 mg/l and a high organicdye compound concentration of 10 mg/l was used, and a metal (platedfilm) was embedded in patterns other than fine interconnect patterns ata current density ranging from 2 to 5 A/dm², finally achieving a platedfilm thickness of 1 μm. By performing the first plating and the secondplating under two-step current conditions, fine patterns can beembedded. By performing the second plating using a plating solutionhaving different additive concentrations, highly smooth plated film wasrealized.

[0074] The method according to the present invention as described abovecan plate a substrate under plating conditions suitable for embeddingboth narrow recesses and broad recesses.

[0075] Therefore, it is possible to form a void-free, high-adhesionplated film of metal such as copper or the like in recesses, thusfabricating a stable-performance semiconductor substrate.

What is claimed is:
 1. A plating method comprising: preparing asubstrate having a relatively narrow recess and a relatively broadrecess defined in a surface thereof; performing first plating underplating conditions for filling a metal in said narrow recess; and thenperforming second plating under plating conditions for filling a metalin said broad recess.
 2. A plating method according to claim 1, whereinentire surfaces of said narrow recess and said broad recess are fullycovered with a seed layer.
 3. A plating method according to claim 1,wherein said first plating is performed under plating conditions for arelatively high bottom-up capability, and said second plating isperformed under plating conditions for a relatively high levelingcapability.
 4. A plating method according to claim 1, wherein saidnarrow recess has a width less than 0.2 μm and said broad recess has awidth of 0.2 μm or greater.
 5. A plating method according to claim 1,wherein said substrate has a plurality of said narrow recesses definedin the surface thereof.
 6. A plating method according to claim 1,wherein said substrate has a plurality of said broad recesses defined inthe surface thereof.
 7. A plating method according to claim 1, whereinsaid first plating and said second plating are performed under platingconditions including different current densities upon plating.
 8. Aplating method according to claim 7, wherein said second plating processis performed under plating conditions including a current density higherthan said first plating.
 9. A plating method according to claim 8,wherein said first plating is performed under plating conditionsincluding a current density upon plating ranging from 0.1 to 1.5 A/dm²,and said second plating is performed under plating conditions includinga current density upon plating ranging from 2 to 7 A/dm².
 10. A platingmethod according to claim 9, wherein said second plating process isperformed with a current density which increases more progressively thansaid first plating.
 11. A plating method according to claim 1, whereinsaid second plating is performed at a higher plating rate than saidfirst plating.
 12. A plating method according to claim 11, wherein saidfirst plating is performed using a copper sulfate plating solutionhaving a large proportion of an accelerator component.
 13. A platingmethod according to claim 12, wherein said accelerator componentcomprises a sulfur-based organic compound.
 14. A plating methodaccording to claim 1, wherein after said first plating is performed, areverse electric field is applied for a short period of time, andthereafter said plating is performed.
 15. A plating method according toclaim 1, wherein said first plating and said second plating areperformed using plating solutions containing different additives addedthereto.
 16. A plating method according to claim 15, wherein theadditive added to the plating solution used in the first plating has arelatively high bottom-up capability, and the additive added to theplating solution used in the second plating has a relatively highleveling capability.
 17. A plating method according to claim 15, whereinthe plating solutions used in said first plating and said second platingcomprise a copper sulfate plating solution, and the plating solutionused in said second plating has a less accelerator component and a moreleveler component than the plating solution used in said first plating.18. A plating method according to claim 1, wherein said first platingand said second plating are performed using plating solutions havingdifferent compositions.
 19. A plating method according to claim 18,wherein the plating solutions used in said first plating and said secondplating comprise a copper sulfate plating solution, and the platingsolution used in said second plating has a lower copper concentrationand a lower sulfuric acid concentration than the plating solution usedin said first plating.
 20. A plating method according to claim 1,wherein said first plating and said second plating are performed underplating conditions including different relative speed of the platingsolution upon plating.
 21. A plating method according to claim 1,wherein an additive added to a plating solution used in the firstplating has a relatively high bottom-up capability, an additive added toa plating solution used in the second plating has a relatively highleveling capability, and a current density in said second plating isgreater than a current density in said first plating.
 22. A platingmethod according to claim 1, wherein plating solutions used in saidfirst plating and said second plating comprise a copper sulfate platingsolution, the plating solution used in said second plating has a lowercopper concentration and a lower sulfuric acid concentration than theplating solution used in said first plating, and a current density insaid second plating is greater than a current density in said firstplating.
 23. A plating method according to claim 1, wherein before saidfirst plating is performed, a voltage is applied between the substrateand an anode which has been in contact with a plating solution beforethe substrate is brought into contact with the plating solution, and thevoltage remains applied and said substrate and said plating solution arebrought into contact with each other.
 24. A plating method according toclaim 23, wherein until said substrate and said plating solution arebrought into full contact with each other, a voltage is applied betweensaid substrate and said anode with a voltage control process whichcontrols the voltage at a predetermined value, and then said firstplating is performed with a current control process which controls acurrent flowing between said substrate and said anode at a predeterminedvalue.
 25. A plating method according to claim 23, wherein until saidsubstrate and said plating solution are brought into full contact witheach other, a voltage is applied between said substrate and said anodewith a voltage control process which controls the voltage at apredetermined value, and then said first plating is performed with avoltage control process which controls a voltage applied between saidsubstrate and said anode at a predetermined value.
 26. A plating methodaccording to claim 1, wherein said first plating and said second platingare performed by an impregnation plating process.